In a growing market demand to improve existing semiconductor device performance on power devices, that is devices that consume a lot of energy such as amplifiers.
Current round or round-like (such as hexagonal or octagonal) solder bump interconnects have become a bottleneck to improve electrical performance to address current flow to the chip level and heat dissipation capability down to the PCB. For example, the “Advanced Connections,” Spring 2002, Advanced Interconnect Technologies, issue describes, inter alia, a pillar bumping interconnect technology that uses perimeter or array flip-chip pads to connect an integrated circuit (IC) to a copper lead frame.
U.S. Pat. No. 6,550,666 B2 to Chew et al. discloses a method for forming a flip chip on leadframe semiconductor package.
U.S. Pat. No. 5,448,114 to Kondoh et al. discloses a semiconductor flip chip packaging having a perimeter wall.
U.S. Pat. No. 6,297,551 B1 discloses integrated circuit packages with improved EMI characteristics.
U.S. Pat. No. 4,430,690 to Chance et al. discloses a low inductance capacitor with metal impregnation and solder bar contact.